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19-0628; Rev 1; 11/06
Single-Phase Synchronous MOSFET Driver
General Description
The MAX8791 is a single-phase synchronous noninverting MOSFET driver. The MAX8791 is intended to work with controller ICs like the MAX8736 or MAX8786, in multiphase notebook CPU core regulators. The regulators can either step down directly from the battery voltage to create the core voltage, or step down from the main system supply. The single-stage conversion method allows the highest possible efficiency, while the 2-stage conversion at higher switching frequency provides the minimum possible physical size. The low-side driver is optimized to drive 3nF capacitive loads with 4ns/8ns typical fall/rise times, and the highside driver with 8ns/10ns typical fall/rise times. Adaptive dead-time control prevents shoot-through currents and maximizes converter efficiency. The MAX8791 is available in a small, lead-free, 8-pin, 3mm x 3mm TQFN package.
Features
Single-Phase Synchronous MOSFET Driver 0.5 Low-Side On-Resistance 0.7 High-Side On-Resistance 8ns Propagation Delay 15ns Minimum Guaranteed Dead Time Integrated Boost "Diode" 2V to 24V Input Voltage Range Selectable Pulse-Skipping Mode Low-Profile TQFN Package
MAX8791
Applications
Notebooks/Desktops/Servers CPU Core Power Supplies Multiphase Step-Down Converters
PART MAX8791GTA+
Ordering Information
TEMP RANGE -40oC to +105oC PINPACKAGE 8 TQFN 3mm x 3mm PKG CODE TQ833+1
+Denotes lead-free package.
Typical Operating Circuit
INPUT (VIN)* 5V TO 24V
Pin Configuration
SKIP
6 LX 7
TOP VIEW
PWM DH
MAX8791
PWM SKIP +5V BIAS SUPPLY SKIP BST LX VDD DL VOUT (1.45V AT 20A)
VDD
5
4 DL
DH 8 +
MAX8791
3 GND
1 BST
2 PWM
GND PAD
TQFN 3mm x 3mm
________________________________________________________________ Maxim Integrated Products
1
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Single-Phase Synchronous MOSFET Driver MAX8791
ABSOLUTE MAXIMUM RATINGS
VDD to GND...................................................... -0.3V to +6V SKIP to GND......................................................-0.3V to +6V PWM to GND .....................................................-0.3V to +6V DL to GND ..................................................-0.3V to (VDD + 0.3V) BST to GND ............................................................-0.3V to +36V DH to LX ....................................................-0.3V to (VBST + 0.3V) BST to VDD .............................................................-0.3V to +30V BST to LX ..........................................................-0.3V to +6V Continuous Power Dissipation 8-Pin 3mm x 3mm TQFN (derate 23.8mW/C above +70C) .............................1904mW Operating Temperature Range .........................-40C to +105C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering 10s) ..................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VDD = SKIP = 5V, TA = -40C to +105C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Input Voltage Range VDD Undervoltage Lockout Threshold SYMBOL VDD VUVLO(VDD) Rising edge, PWM disabled below this level Falling edge, PWM disabled below this level PWM = open; after the shutdown hold time has expired Quiescent Supply Current (VDD) DRIVERS PWM Pulse Width DL Propagation Delay DH Propagation Delay DL-to-DH Dead Time DH-to-DL Dead Time DL Transition Time DH Transition Time DH Driver On-Resistance DL Driver On-Resistance DH Driver Source Current DH Driver Sink Current DL Driver Sink Current Zero-Crossing Threshold Boost On-Resistance tON(MIN) tOFF(MIN) tPWM-DL tPWM-DH tDL-DH tDH-DL tF_DL tR_DL tF_DH tR_DH RON(DH) RON(DL) Minimum on-time Minimum off-time PWM high to DL low PWM low to DH low DL falling to DH rising DH falling to DL rising Falling, 3.0nF load Rising, 3.0nF load Falling, 3.0nF load Rising, 3.0nF load BST-LX forced to 5V DL, high state (pullup) DL, low state (pulldown) DH forced to 2.5V, BST - LX forced to 5V DL forced to 2.5V GND - LX, SKIP = GND VDD = 5V, DH = LX = GND (pulldown state), IBST = 10mA DH, high state (pullup) DH, low state (pulldown) TA = 0C to +85C TA = -40C to +105C TA = 0C to +85C TA = -40C to +105C 15 15 15 15 12 14 8 10 0.9 0.7 0.7 0.5 2.2 2.7 2.7 8 3 5 12 2.5 2.3 1.8 1.2 30 50 300 10 14 30 ns ns ns ns ns ns ns A A A A mV IDD SKIP = GND, PWM = GND, LX = GND (after zero crossing) SKIP = GND or VDD, PWM = VDD, VBST = 5V 3.0 CONDITIONS MIN 4.20 3.7 3.5 0.08 0.25 0.6 4.0 0.2 0.5 1.5 mA TYP MAX 5.50 UNITS V V
IDH_SOURCE DH forced to 2.5V, BST - LX forced to 5V IDH_SINK IDL_SINK VZX RON(BST)
DL Driver Source Current IDL_SOURCE DL forced to 2.5V
2
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Single-Phase Synchronous MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDD = SKIP = 5V, TA = -40C to +105C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS High (DH = high; DL = low) PWM Input Levels Midlevel Low (DH = low; DL = high) PWM Input Current Midlevel Shutdown Hold Time SKIP Input Threshold SKIP Input Current Thermal-Shutdown Threshold ISKIP TSHDN IPWM tMID Rising edge Falling edge Sink; SKIP forced to 0.8V to VDD, TA = +25C Hysteresis = 20C 0.8 -4 Sink; PWM forced to VDD Source; PWM forced to GND -400 80 120 -200 +200 300 1.7 1.5 -2 +160 -0.5 MIN VDD 0.4 VDD / 2 - 0.4 VDD / 2 + 0.4 0.4 -80 400 600 2.4 A ns V A C V TYP MAX UNITS
MAX8791
Note 1: Limits are 100% production tested at TA = +25C. Maximum and minimum limits over temperature are guaranteed through correlation using statistical-quality-control (SQC) methods.
Typical Operating Characteristics
(Circuit of Figure 1, VDD = 5V, CDH = 3nF, CDL = 3nF, TA = +25C, unless otherwise noted.)
PACKAGE-POWER DISSIPATION vs. PWM FREQUENCY
MAX8791 toc01
PACKAGE-POWER DISSIPATION vs. CAPACITIVE LOAD ON DH AND DL
MAX8791 toc02
DL RISE AND FALL TIMES vs. CAPACITIVE LOAD
MAX8791 toc03
300 250 B 200 PD (mW) A 150 100 50 0 0 200
500 450 400 350 PD (mW) 300 250 200 150 100 A A: 300kHz B: 600kHz C: 1MHz 1000 2500 4000 5500 7000 CAPACITANCE (pF) B C
30 25 RISE AND FALL TIME (ns) RISE TIME 20 15 10 FALL TIME 5 CDL = CDH 0 1000 2500 4000 5500 7000 CAPACITANCE (pF)
A: CDH = 3.3nF; CDL = 3.3nF B: CDH = 1.5nF; CDL = 6.8nF 400 600 800 1000 PWM FREQUENCY (kHz) 1200
50 0
8500 10,000
8500 10,000
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Single-Phase Synchronous MOSFET Driver MAX8791
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VDD = 5V, CDH = 3nF, CDL = 3nF, TA = +25C, unless otherwise noted.)
DH RISE AND FALL TIMES vs. CAPACITIVE LOAD
MAX8791 toc04
DH AND DL RISE AND FALL TIMES vs. TEMPERATURE
MAX8791 toc05
PACKAGE-POWER DISSIPATION vs. PWM FREQUENCY
B 50 A 40 IDD (mW)
MAX8791 toc06
40 35 RISE AND FALL TIME (ns) 30 25 20 FALL TIME 15 10 5 CDL = CDH 0 1000 2500 4000 5500 7000 CAPACITANCE (pF) RISE TIME
40 DL RISE 35 RISE AND FALL TIME (ns) 30 DH RISE 25 DH FALL 20 DL FALL 15 10 DL IS DRIVING 2 SI7336ADP DH IS DRIVING 1 SI7892ADP -40 -15 10 35 60 TEMPERATURE (C) 85
60
30 20 10 0
A: CDH = 3.3nF; CDL = 3.3nF B: CDH = 1.5nF; CDL = 6.8nF 0 200 400 600 800 1000 PWM FREQUENCY (kHz) 1200
8500 10,000
110
PROPAGATION DELAY TIME vs. TEMPERATURE
15 PROPOGATION DELAY TIME (ns) 14 13 12 11 10 9 VDH 8 -40 -15 10 35 60 TEMPERATURE (C) 85 110 PWM RISE TO DL FALL VDL VLX PWM FALL TO DH FALL
MAX8791 toc07
TYPICAL APPLICATION CIRCUIT SWITCHING WAVEFORMS
MAX8791 toc08
16
VPWM
5V/div
10V/div
5V/div
20V/div 100ns/div
DH FALL AND DL RISE WAVEFORMS
MAX8791 toc09
DH RISE AND DL FALL WAVEFORMS
MAX8791 toc10
VPWM
5V/div
VPWM
5V/div
VLX
10V/div
VLX
10V/div
VDL
5V/div
VDL
5V/div
10V/div VDH 20ns/div
10V/div VDH 20ns/div
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Single-Phase Synchronous MOSFET Driver
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VDD = 5V, CDH = 3nF, CDL = 3nF, TA = +25C, unless otherwise noted.)
MAX8791
SWITCHING WAVEFORMS (PWM = MID TO LOW TO MID)
MAX8791 toc11
SWITCHING WAVEFORMS (PWM = HIGH TO MID TO HIGH)
MAX8791 toc12
VPWM
5V 5V/div 0 5V 5V/div 0 0 10V/div
VPWM VDL
5V 5V/div 0 0 5V/div 10V 10V/div 0 15V
VDL
VLX
VLX
VDH
0 10V/div
VDH
10V/div 0
Pin Description
PIN 1 NAME BST FUNCTION Boost Flying-Capacitor Connection. Gate-drive power supply for DH high-side gate driver. Connect a 0.1F or 0.22F capacitor between BST and LX. PWM Input Pin. Noninverting DH control input from the controller IC: Logic high: DH = high (BST), DL = low (PGND). Midlevel: After the midlevel hold time expires, the controller enters standby mode. DH and DL pulled low. Logic low: DH = low (LX), DL = high (VDD) when SKIP = high. Internal pullup and pulldown resistors create the midlevel and prevent the controller from triggering an on-time if this input is left unconnected (not soldered properly) or driven by a high impedance. Power Ground for the DL Gate Drivers and Analog Ground. Connect exposed pad to GND. PWM Low-Side Gate-Driver Output. Swings between GND and VDD. DL forced high in shutdown. Supply Voltage Input for the DL Gate Drivers. Connect to 4.2V to 5.5V supply and bypass to GND with a 1F ceramic capacitor. Pulse-Skipping Mode Pin. Enable pulse-skipping mode (zero-crossing comparator enabled) when the driver is operating in SKIP mode: SKIP = VDD PWM mode SKIP = GND SKIP mode An internal pulldown current pulls the controller into the low-power pulse-skipping state if this input is left unconnected (not soldered properly) or driven by a high impedance. Switching Node and Inductor Connection. Low-power supply for the DH high-side gate driver. LX connects to the skip-mode zero-crossing comparator. External High-Side nMOSFET Gate-Driver Output. Swings between LX and BST. Exposed Pad. Connect to ground through multiple vias to reduce the thermal impedance.
2
PWM
3 4 5
GND DL VDD
6
SKIP
7 8 --
LX DH EP
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Single-Phase Synchronous MOSFET Driver MAX8791
PWM
DH BST CBST 0.1F CDH 3nF
PWM
SKIP
SKIP
MAX8791
LX
DL +5V BIAS SUPPLY
CDL 3nF
VDD C1 1.0F PAD
GND
Figure 1. Test Circuit
tPWM-DL tMID
tPWM-DH
tMID tPWM-DL
PWM tF_DL DL tR_DL tF_DL tR_DL
tDL-DH
tDH-DL
DH tR_DH tPWM-DH
tR_DH
tR_DH
tR_DH
Figure 2. Timing Diagram
6 _______________________________________________________________________________________
Single-Phase Synchronous MOSFET Driver MAX8791
INPUT (VIN) CIN 2x 10F
PWM
DH
NH
PWM +5V BIAS SUPPLY
SKIP
SKIP
BST
CBST 0.22F
L1 0.36H OUTPUT (VOUT) COUT 2x 330F 6m
MAX8791
VDD CVDD 1.0F
LX
DL
NL
DL
GND PAD
Figure 3. Typical MOSFET-Driver Application Circuit
Table 1. Typical Components
DESIGNATION NH NL BST Capacitor (CBST) Schottky Diode Inductor (L1) Output Capacitors (COUT) Input Capacitors (CIN) QTY 1 per phase 1-2 per phase 1 per phase Optional 1 per phase 1-2 per phase 1-2 per phase COMPONENT SUPPLIERS Siliconix Si4860DY Siliconix Si4336DY 0.1F or 0.22F ceramic capacitor 3A, 40V Schottky diode 0.36H, 26A, 0.9m power inductor 330F, 6m per phase 10F, 25V X5R ceramic capacitors
Detail Description
The MAX8791 single-phase gate driver, along with the MAX8736 or MAX8786 multiphase controllers, provide flexible multiphase CPU core-voltage supplies. The low driver resistance allows up to 7A output peak current. Each MOSFET driver in the MAX8791 is capable of driving 3nF capacitive loads with only 9ns propagation delay and 4ns/8ns (typ) fall/rise times, allowing operation up to 3MHz per phase. Larger capacitive loads are allowable but result in longer propagation and transition times. Adaptive dead-time control prevents shootthrough currents and maximizes converter efficiency while allowing operation with a variety of MOSFETs and PWM controllers. An input undervoltage lockout (UVLO) circuit allows proper power-on sequencing.
PWM Input
The drivers for the MAX8791 are disabled--DH and DL pulled low--if the PWM input remains in the midlevel window for at least 300ns (typ). Once the PWM signal is driven high or low, the MAX8791 immediately exits the low-current shutdown state and resumes active operation. Outside the shutdown state, the drivers are enabled based on the rising and falling thresholds specified in the Electrical Characteristics.
MOSFET Gate Drivers (DH, DL)
The high-side driver (DH) has a 0.9 sourcing resistance and 0.7 sinking resistance, resulting in 2.2A peak sourcing current and 2.7A peak sinking current with a 5V supply voltage. The low-side driver (DL) has a typical 0.7 sourcing resistance and 0.3 sinking resistance, yielding 2.7A peak sourcing current and 8A peak sinking current. This reduces switching losses,
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Single-Phase Synchronous MOSFET Driver MAX8791
VDD BST PWM DRIVER LOGIC AND DEAD-TIME CONTROL
DRV
DH
THERMAL SHUTDOWN
LX
UVLO DRV# VDD SKIP DL
LX ZX DETECTION
GND
PAD
Figure 4. Overview Block Diagram
making the MAX8791 ideal for both high-frequency and high output-current applications.
Adaptive Shoot-Through Protection The DH and DL drivers are optimized for driving moderately sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in the notebook CPU environment, where a large VIN - VOUT differential exists. Two adaptive dead-time circuits monitor the DH and DL outputs and prevent the opposite-side FET from turning on until the other is fully off. The MAX8791 constantly monitors the low-side driver output (DL) voltage, and only allows the high-side driver to turn on only when DL drops below the adaptive threshold. Similarly, the controller monitors the high-side driver output (DH), and prevents the low side from turning on until DH falls below the adaptive threshold before allowing DL to turn on.
The adaptive driver dead time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency. There must be a low-resistance, low-inductance path from the DL and DH drivers to the MOSFET gates for the adaptive dead8
time circuits to work properly; otherwise, the sense circuitry in the MAX8791 interprets the MOSFET gates as off while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver).
Internal Boost Switch
The MAX8791 uses a bootstrap circuit to generate the necessary drive voltage to fully enhance the high-side n-channel MOSFET. The internal p-channel MOSFET creates an ideal diode, providing a low voltage drop between VDD and BST. The selected high-side MOSFET determines appropriate boost capacitance values (CBST in Figure 1), according to the following equation: CBST = QGATE / VBST where QGATE is the total gate charge of the high-side MOSFET and VBST is the voltage variation allowed on the high-side MOSFET driver. Choose VBST = 0.1V to 0.2V when determining CBST. The boost flying capacitor
_______________________________________________________________________________________
Single-Phase Synchronous MOSFET Driver
should be a low equivalent-series resistance (ESR) ceramic capacitor. (reducing RDS(ON) but increasing CGATE). Conversely, if the losses at VIN(MAX) are significantly higher than the losses at VIN(MIN), consider reducing the size of NH (increasing RDS(ON) but reducing CGATE). If VIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. Choose a low-side MOSFET that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., one or two 8-pin SOs, DPAK, or D2PAK), and is reasonably priced. Ensure that the DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems can occur.
MAX8791
5V Bias Supply (VDD) VDD provides the supply voltage for the internal logic circuits. Bypass VDD with a 1F or larger ceramic capacitor to GND to limit noise to the internal circuitry. Connect these bypass capacitors as close as possible to the IC.
Input Undervoltage Lockout When VDD is below the UVLO threshold, DH and DL are held low. Once VDD is above the UVLO threshold and while PWM is low, DL is driven high and DH is driven low. This prevents the output of the converter from rising before a valid PWM signal is applied.
Low-Power Pulse Skipping
The MAX8791 enters into low-power pulse-skipping mode when SKIP is pulled low. In skip mode, an inherent automatic switchover to pulse-frequency modulation (PFM) takes place at light loads. A zero-crossing comparator truncates the low-side switch on-time at the inductor current's zero crossing. The comparator senses the voltage across LX and GND. Once V LX - V GND drops below the zero-crossing comparator threshold (see the Electrical Characteristics), the comparator forces DL low. This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation. The PFM/PWM crossover occurs when the load current of each phase is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value. For a battery input range of 7V to 20V, this threshold is relatively constant, with only a minor dependence on the input voltage due to the typically low duty cycles. The switching waveforms may appear noisy and asynchronous when light loading activates the pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the minimum input voltage: V I PD (NH RESISTIVE) = OUT LOAD RDS(ON) VIN TOTAL where TOTAL is the total number of phases. Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package-power dissipation often limits how small the MOSFETs can be. Again, the optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. High-side switching losses do not usually become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFETs (NH) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for prototype evaluation, preferably including verification using a thermocouple mounted on NH:
VIN(MAX)ILOADfSW QG(SW) PD (NH SWITCHING) = + nTOTAL IGATE COSSVIN2fSW 2
2
Applications Information
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both V IN(MIN) and V IN(MAX) . Calculate both these sums. Ideally, the losses at VIN(MIN) should be roughly equal to losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the size of NH
_______________________________________________________________________________________
9
Single-Phase Synchronous MOSFET Driver MAX8791
where COSS is the NH MOSFET's output capacitance, QG(SW) is the charge needed to turn on the high-side MOSFET, and IGATE is the peak gate-drive source/sink current (5A typ). Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied due to the squared term in the switching-loss equation above. If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when biased from VIN(MAX), consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at the maximum input voltage:
2 V I PD (NL RESISTIVE) = 1 - OUT LOAD RDS(ON) VIN(MAX) TOTAL
where PD(IC) is the power dissipated by the device, and JA is the package's thermal resistance. The typical thermal resistance is 42C/W for the 3mm x 3mm TQFN package.
Avoiding dV/dt Turning on the Low-Side MOSFET
At high input voltages, fast turn-on of the high-side MOSFET can momentarily turn on the low-side MOSFET due to the high dV/dt appearing at the drain of the lowside MOSFET. The high dV/dt causes a current flow through the Miller capacitance (CRSS) and the input capacitance (CISS) of the low-side MOSFET. Improper selection of the low-side MOSFET that results in a high ratio of CRSS/CISS makes the problem more severe. To avoid this problem, minimize the ratio of CRSS/CISS when selecting the low-side MOSFET. Adding a 1 to 4.7 resistor between BST and C BST can slow the high-side MOSFET turn-on. Similarly, adding a small capacitor from the gate to the source of the high-side MOSFET has the same effect. However, both methods work at the expense of increased switching losses.
The worst case for MOSFET power dissipation occurs under heavy load conditions that are greater than ILOAD(MAX), but are not quite high enough to exceed the current limit and cause the fault latch to trip. The MOSFETs must have a good-sized heatsink to handle the overload power dissipation. The heat sink can be a large copper field on the PCB or an externally mounted device. An optional Schottky diode only conducts during the dead time when both the high-side and low-side MOSFETs are off. Choose a Schottky diode with a forward voltage low enough to prevent the low-side MOSFET body diode from turning on during the dead time, and a peak current rating higher than the peak inductor current. The Schottky diode must be rated to handle the average power dissipation per switching cycle. This diode is optional and can be removed if efficiency is not critical.
Layout Guidelines
The MAX8791 MOSFET driver sources and sinks large currents to drive MOSFETs at high switching speeds. The high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. The following PCB layout guidelines are recommended when designing with the MAX8791: 1) Place all decoupling capacitors as close as possible to their respective IC pins. 2) Minimize the length of the high-current loop from the input capacitor, the upper switching MOSFET, and the low-side MOSFET back to the input-capacitor negative terminal. 3) Provide enough copper area at and around the switching MOSFETs and inductors to aid in thermal dissipation. 4) Connect GND of the MAX8791 as close as possible to the source of the low-side MOSFETs. A sample layout is available in the MAX8786 evaluation kit.
IC Power Dissipation and Thermal Considerations
Power dissipation in the IC package comes mainly from driving the MOSFETs. Therefore, it is a function of both switching frequency and the total gate charge of the selected MOSFETs. The total power dissipation when both drivers are switching is given by: PD(IC) = IBIAS x 5V where IBIAS is the bias current of the 5V supply calculated in the 5V Bias Supply (VDD) section. The rise in die temperature due to self-heating is given by the following formula: TJ = JA x PD(IC)
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Chip Information
TRANSISTOR COUNT: 1228 PROCESS: BiCMOS
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Single-Phase Synchronous MOSFET Driver
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
12x16L QFN THIN.EPS
MAX8791
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
(c) 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
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